1. Field of Invention
The present invention relates to electronic field, and more particularly, relates to a reliable charge pump circuit which can ensure proper functionality in all conditions.
2. Description of Related Arts
Both Phase-Locked Loop (PLL) and Delay Locked Loop (DLL), require to obtain a phase difference between their own output signal and input reference signal, then integrate this phase difference via a charge pump circuit, and the integrated result is reflected in control voltage VCTRL in form of varying quantity of voltage. The control voltage VCTRL is used to control a voltage controlled oscillator VCO or a voltage controlled delay line VCDL, until their phases are synchronous. The system to achieve above phase-locked loop lock process (PLL) is shown in FIG. 1.
The relevant reference is the following U.S. patents:
CHARGE PUMP CIRCUIT
U.S. Pat. No. 6,535,051 B2 March 2003 Kyu-hyoun Kim
HIGH OUTPUT IMPEDENCE CHARGE PUMP FOR PLL/DLL
U.S. Pat. No. 7,176,733 B2 February 2007 Dieter Haerle
During this process, if the output voltage of the charge pump is locked on a certain value owing to some reasons such as circuit's positive feedback, or existence of multiple stable status, the process for tracking and locking the frequency of the input signal will fail. On the other hand, if the phase margin of the feedback loop is not enough, that is, the phase of the loop gain is larger than 135 degree when the magnitude of the loop gain is unity, then the whole feedback loop will oscillate, and the charge pump could not work properly.
The startup and stability issues caused by the charge pump circuit are as listed below.
As shown in FIG. 2, the traditional charge pump circuit has the following problems: in the process of startup or normal work, once the voltage of net OUT is higher the voltage of the net14, it is likely to occur positive feedback to make the charge pump work improperly, that is, when the voltage of net OUT is higher than the voltage of the net14, under the effect of the Operational Amplifier 113, the voltage of the net15 decreases below the NMOS transistor's threshold voltage Vthn, then the NMOS transistors 107, 109 will be cut-off, and both the voltages of net OUT and net14 will be elevated until being near a certain voltage value, at this certain voltage value, due to cut-off of the PMOS transistors 104, 106, the voltages of net OUT and net14 stop elevating. It is noted that the certain voltage value is one threshold value of PMOS transistor less than the net16.
Firstly, if at the end of the above process, the voltage of the net OUT is higher than the voltage of the net14, the final state is the NMOS transistors 107, 109 and the PMOS transistors 104, 106 will be all cut-off, that is, the state that the voltage of the net OUT is higher than the voltage of the net14 keeps being locked up, so that the charge pump could not work properly.
Secondly, even if at the end of the process the voltage of the net OUT is less than the voltage of the net14, then under the effect of the Operational Amplifier 113, the net15 is elevated, due to the effect of the NMOS transistors 107, 109, the voltages of the net OUT and the net14 will decrease, and once the net OUT is higher than the voltage of the net14, the process described above will repeat again to cause oscillation. In other words, the operational amplifier 113 and the NMOS transistors 107,109 form a negative feedback loop and a positive feedback loop. Making a small signal analysis for entire circuit system, once the phase margin of the negative feedback loop is not enough, the system will oscillate, and the charge pump will not work properly.
Furthermore, if adding a startup circuit in the charge pump circuit, that is, NMOS transistors 111, 112, which make sure that the net OUT is lower than the voltage of the net14 during startup process. However, once there are some disturbances making the net OUT higher than the voltage of the net14 during working process, the problem described above will still occur.
Making a small signal analysis, the open-loop transferring function of the negative feedback loop is obtained from an equivalent circuit of small signal as shown in FIG. 4, which can be expressed by the following Equation:
            Vout      Vin        ⁢          (      s      )        =                              G          ⁢                                          ⁢                      1            ·            R                    ⁢                                          ⁢          1                          1          +                      R            ⁢                                                  ⁢                          1              ·              C                        ⁢                                                  ⁢            1            ⁢            s                              ·                        G          ⁢                                          ⁢                      2            ·            R                    ⁢                                          ⁢          2                          1          +                      R            ⁢                                                  ⁢                          2              ·              C                        ⁢                                                  ⁢            2            ⁢            s                                =                            G          ⁢                                          ⁢                      1            /            C                    ⁢                                          ⁢          1                          s          +                      1            /                          (                              R                ⁢                                                                  ⁢                                  1                  ·                  C                                ⁢                                                                  ⁢                1                            )                                          ·                                    G            ⁢                                                  ⁢                          2              /              C                        ⁢                                                  ⁢            2                    ⁢                                                          s          +                      1            /                          (                              R                ⁢                                                                  ⁢                                  2                  ·                  C                                ⁢                                                                  ⁢                2                            )                                          
here, W1=1/(R1·C1), W2=1/(R2·C2), because the two poles are approximately equal to each other, resulting that the phase margin is not enough, so the entire system is not stable.